Data prefetching has emerged as a critical approach to mitigate the performance bottlenecks imposed by memory access latencies in modern computer architectures. By predicting the data likely to be ...

This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced ...

A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.