GitHub

tomasulo-algorithm

A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz. Simulation of the Tomasulo algorithm using python ...
GitHub

Tomasulo Algorithm Pipelined Processor

In this project, we construct a simulator for an out-of-order superscalar processor that uses the Tomasulo algorithm and fetches F instructions per cycle. We design the simulator to maintain ...
IEEE

Design and implementation of low power reservation station of a 32-bit DLX-RISC processor

Abstract: This paper presents the implementation of a reservation station used in a 32-bit DLX RISC processor using Tomasulo algorithm on 20nm and 28nm FPGA boards and compares the results for power, ...
EDN

Tomasulo Out of Order Processor Design

(VHDL, ModelSim, Xilinx) Simulated and synthesized a processor with a clock frequency of 25 MHz. Used Tomasulo algorithm to dynamically schedule instructions and execute them in out of program order ...